Master Thesis: Configurable Access Policies for Hardware Priority Queue Schedulers

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About this opportunity:

Hardware task schedulers are key components in heterogeneous computing platforms such as network processors, baseband accelerators, and GPU command processors. A common pattern is the multi-queue priority scheduler: a hardware block managing many priority queues from which processing elements (PEs) request work items.

This thesis aims to address that gap by developing a diagnostic observability layer that integrates with the existing UVM performance environment and converts each sub-par point on a performance curve into a localized, actionable root-cause explanation. The layer is intended to automatically capture where stalls occur, under which conditions, and from which internal or external source, so that performance debugging becomes early, repeatable, and conclusive rather than a manual end-stage effort carrying high rework risk. A secondary track can extend this to dataset design for AI-parseable stall analysis.

This thesis investigates the design space between rigid static access modes and fully software-managed scheduling. The central question is: given ASIC implementation constraints, which forms of access policy configurability yield meaningful performance or efficiency improvements, and at what cost?

The work is anchored in modeling and empirical evaluation. Candidate policies are assessed both in terms of functional performance (throughput, arbitration latency, fairness) through high-level modeling, and in terms of implementation cost (silicon area, critical path timing, power) through RTL synthesis. The goal is actionable design guidance — characterizing when configurability helps, when it doesn't, and how much flexibility is "enough" for representative workload classes.

What you will do:

• Pursuing a master’s in Electrical/Computer Engineering, Computer Science, Embedded Systems, or a related field.

• Knowledge of computer architecture and ASIC design.

• Experience with RTL HDL coding and testbench development using SystemVerilog.

• Working knowledge of UVM and scripting (Tcl/Python) for EDA tool flows.

• Interest in performance evaluation, modeling, and empirical analysis.

• Interest and/or experience in AI is a plus.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791273