- Location
- San Diego, CA,US, US · Santa Clara, CA,US, US · Austin, TX,US, US
- Workplace
- Hybrid
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Education
- PhD
- Source
- Eightfold
Description
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Bachelors degree in Science, Engineering, or closely related field 1+ years of hands on experience in emulation/simulation acceleration/FPGA. 1+ years in Design validation/Post-Silicon debug. 1+ years of hands on experience in creating high performance & area efficient emulation environments from RTL. 1+ years of hands on emulator platforms, platform bringup, digital design, verification, debugging, and waveform viewers 1+ Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs 1+ Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration MS degree in Electrical Engineering or equivalent; 1 year of practical experience Design Verification knowledge - UVM/System Verilog preferred Knowledge of GPU/CPU/DDR/Bus preferred Verilog and System Verilog experience. Debugging system-level software, Debug RTL Programming skills in C and C++ Scripting in Python, Tcl, or Perl Knowledge of Vendor Emulation tools/Xilinx tools/Synthesis tools Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance. Work with designers and SW driver team for testplan and debug. Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL. Work on third-party IP integration and system-level debugging. Support chip bring up and post silicon debug.
