About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

 

About the Role

As a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation of our next-generation IPs. You will be responsible for translating complex RTL into high-performance implementation, ensuring architecture/design achieves its absolute peak physical potential.

We are looking for a true "full-stack" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath choices affect congestion, how a memory floorplan impacts PPA, and how to push the boundaries of Power, Performance, and Area (PPA) through cross-functional collaboration.

Key Responsibilities - What you’ll do

• End-to-End Implementation: Drive the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.

• Architectural & RTL Co-Optimization: Actively partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early—such as routing congestion in complex crossbars, dynamic power hot-spots in execution units, and interconnect span limits—and co-design microarchitectural or structural solutions to overcome them.

• Cross-Product PPA Push: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes driving extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.

• Technical Leadership: Act as the subject matter expert for complex implementation challenges; contribute to flows/methodology/automation; mentor junior engineers and champion best practices.

Requirements - What you’ll bring

• Experience: 8+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced process nodes (7nm and below preferred).

• Versatile IP Implementation Expertise: Deep familiarity with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.

• Co-Design Mindset: A strong understanding of how physical design choices influence microarchitecture, with the intellectual curiosity to pick up the specific nuances of diverse product lines.

• Tool Mastery: Expert-level proficiency with industry-standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.

• Advanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion, and dynamic IR drop with minimal supervision.

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Why join us?

In this role, you will be pivotal in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio from highly efficient IoT cores, dense memory systems, and demanding high-performance platforms. We offer the opportunity to collaborate with world-class engineers in a supportive, fast-paced, and learning-rich environment.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.