Senior Engineer Runsets Development for Mask Data Preparation and Tapeout Enablement (f/m/div)

#WeAreIn for jobs that impact

everyone's life. Join the thinkers, builders,

and problem-solvers behind tomorrow’s technology. As a  Senior Engineer Runsets Development for Mask Data Preparation and Tapeout

Enablement (f/m/div)  on our Research & Development

team, you'll have the opportunity to merge creativity with your technical

expertise by shaping the future of technology, driving groundbreaking projects,

and bringing new ideas to life. Are you in? Your role Key responsibilities in your new role Design, develop, validate, and drive the continuous improvement of Mask Data

Preparation (MDP) runsets, including fracturing, proximity correction pre-processing, data format conversion, and mask rule checking (MRC) Develop and maintain OPC (Optical Proximity Correction) and ILT (Inverse Lithography

Technology) runsets in collaboration with lithography, process development and integration teams Create and own DRC (Design Rule Check) and DFM (Design for Manufacturability) run sets supporting flows and sign-off criteria for internal and foundry-based tapeouts Maintain runset version control , documentation , and enforce runset quality metrics ,  regression testing frameworks , and  release validation procedures by supporting continuous improvement initiatives to reduce tapeout cycle time ,  improve data

quality , and enhance runset robustness Serve as technical interface to fabs (internal and external), Design  and IP Teams on

MDP run set methodology , flow architecture and best practices Drive automation  and scripting initiatives  to improve runset development efficiency,

regression testing, and deployment Your profile Qualifications and skills to help you succeed     A degree in Electrical Engineering , Computer Engineering , Physics , or a related

field At least 5+ years of experience in semiconductor process technology, EDA, or design technology with direct involvement in MDP and/or tapeout flows Many years of hands-on experience in developing and qualifying MDP runsets , DRC

decks and OPC runsets at advanced technology nodes Proficiency with industry-standard EDA tools including one or more of: Siemens EDA (Calibre) – xRC, DRC, LVS, OPCpro, MDPview; Synopsys –IC Validator, Proteus OPC, Sentaurus Lithography and Cadence – Pegasus, Physical Verification S trong

programming and scripting skills in SVRF, TVF, Python, Perl, TCL, or SKILL and strong cross-functional communication skills , with the ability to present

technical concepts clearly to diverse audiences Ability to manage multiple priorities in a fast-paced, deadline-driven tapeout environment and strong collaboration and partnership skills with internal teams and external foundry/vendor partners Familiarity

with curvilinear mask data formats and next-generation mask writing is a plus Fluent English (written and spoken); German is a plus #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.  Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Jara Bremicker https://www.linkedin.com/in/jara-bremicker-b49056225/