ASIC 3D DRAM Architect

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. The candidate will assess and optimize the 3D DRAM architecture to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will explore the best organization of near-memory processing units along with the system and memory buses so that the extreme bandwidth of 3D DRAM will be fully utilized across the compute fabric for cloud, compute, mobile and IoT. The candidate will work on solutions addressing manufacturability and repairability of both DRAM and compute fabric. The candidate is expected to understand the concepts of DRAM bank organization and signaling, bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential. Experience in ASIC design, mixed-signal design, and performance modeling Good knowledge of memory architecture, buses, and 2.5D/3D integration Proficiency in use of EDA tools, Matlab, and Phyton Master's or Ph.D. in Electrical Engineering, Computer Science, or a related field Experience in circuit and system design to be able to model and optimize dataflow Experience in DRAM architecture performance assessment Experience in memory circuit design (SRAM/DRAM/Flash/ROM/OPT, etc) Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow is strong plus Familiar with the DRAM datasheets and IO interfaces Self-Starter with good communication skills and team-working spirit Strong problem-solving and analytical skills Ability to work independently and as part of a team Develop and optimize 3D DRAM bank organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W Develop and validate models for 3D DRAM performance, power, and yield as function of bank, TSV, and power distribution choices Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications Develop power distribution topology that enable robust DRAM operation in the 3D stack Simulate and emulate system performance of 3D DRAM architecture choices across AI, compute, and mobile workloads Floorplan 3D DRAM chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance