SoC Physical Design Senior Manager, HBM

Req ID:

JR110799 SoC Physical Design Senior Manager, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.

Key Responsibilities

• Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
• Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
• Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
• Drive agentic AI development initiatives and develop AI/LLM driven workflows.

Required Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
• Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
• Ability to work in a global, cross-functional environment with strong communication and debugging skills.
• Experience implementing AI flows and using agentic AI and LLMs.

Preferred Qualifications

• Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Job Profile(s):

Systems Design Engineer Manager 2

Relocation Level: TBD

Before Getting Started

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The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$177,000.00 - $309,000.00 a year

Additional compensation may include benefits, bonuses and equity.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

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