- Location
- IND - Karnataka - Bengaluru - Central, India
- Type
- Full-time
- Department
- Engineering
- Source
- Workday
Description
Your Job
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features under manager guidance.
Execute test pattern generation and optimization to minimize test time while maximizing coverage and manufacturing yield.
Apply standardized DFT methodologies and flows to deliver efficient, repeatable results across multiple projects.
Integrate DFT requirements into RTL and physical design stages through collaboration with design, verification, and backend teams.
Develop automation scripts (TCL, Python, Perl) for test pattern creation, validation, and analysis.
Analyze test data from silicon bring-up and production to identify improvements and support root-cause debugging.
Document DFT implementations, test results, and reuse IP for team knowledge sharing.
Other Responsibilities
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
4+ years of hands-on DFT experience on SoCs, including ATPG, MBIST, LBIST, and scan-based testing.
Proficiency with EDA tools such as Synopsys TestMAX, Cadence Modus, or Mentor Tessent for DFT insertion and pattern generation.
Experience with scripting languages (Python, Perl, TCL) for flow automation and data analysis.
Familiarity with optimizing test time, fault coverage, and ATPG patterns.
Strong analytical skills and attention to detail for debugging complex test failures.
Effective communication skills for cross-functional collaboration.
Preferred Qualifications
Experience with automotive ASIL flows or high-volume manufacturing test challenges.
Proactive contributor to process improvements and tool evaluations.
Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia