UVM Verification specialist for ASIC and/or FPGA development

AFRY

•

Apr 23, 2026

Pune, MH, IndiaHybridFull-timeElectronics System and Communication technologyMid-Senior Level

Skills & Technologies

PythonPerl

Ready to apply?

Opens AFRY's career page

Similar Jobs

12

Design Verification Engineer - UVM, Verilog (5 to 8 yrs)

IND-BANGALORE, India

Principal Firmware Verification Engineer - UVM (Onsite)

US-MA-MARLBOROUGH-MA2 ~ 1001 Boston Post Rd ~ BLDG 2, United States of America

Engineer – FPGA Verification (SV-UVM)

Bangalore Anchorage, India

FPGA Verification Engineer - UVM Architect

"Quest Defense Systems & Solutions, Inc."

Remote +1 more

ASIC Design Verification Engineer | UVM | Exp 8+ Years

IND-BANGALORE, India

ASIC Design Verification Engineer | UVM | Exp. 8+ years

IND-BANGALORE, India

Senior UVM Digital Verification Engineer

MA - Cambridge, United States of America

UVM Digital Verification Engineer

MA - Cambridge, United States of America

ASIC Design Verification Engineer | UVM | Exp- 8+ Years

IND-BANGALORE, India

ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

IND-BANGALORE, India

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

IND-PUNE, India

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

IND-PUNE, India