Staff Engineer, Design

Req. ID:

JR113232 Staff Engineer, Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description:

As a Design Engineer for Non-Volatile Memory Datapath Functional Group at Micron, you will support design and validation activities of Datapath and DDR high-speed interfaces of Flash Memory (non-volatile memory) products. Prior experience in Plane Datapath Design is a plus. In this highly challenging role, you will be engaged in high-speed circuits block level and sub-system level design and timing optimization and supervising their layout.

You will be working with project/cross-functional teams to understand full chip floor plan and how to fit and place your circuits at full chip level. You will be also working with Application Engineering team to understand the new specs and translate them into circuit requirements. You will also work with CMOS/modeling team to define CMOS characteristics to realize and enable high-speed circuits. In addition to design activities, you will be heavily engaged in high-speed circuits functional and timing validation from base cells all the way to full-chip level using wide variety of simulation tools such as HSPICE, Fast SPICE and NC Verilog.

Having 'Design/Verification + AI' approach accelerates the design process. So, you should be able to adept to ‘Design + AI’ approach with Novel ideas which improves the productivity/Performance.

You are also responsible for documenting block level and sub-system level Micro-Architecture Spec (MAS) in accordance with variety of industry standards such as ISO26262. A deep understanding and knowledge of high frequency digital, analog and mixes signal circuit design, CMOS device physics, CMOS circuits power consumption concepts and pipeline structures are necessary.

Skills required:

• Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (5 – 40 nm) in High-speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes. Having Plane Datapath design is a big plus. Candidate must have experience in Parallel or Serial Interface.
• Alongside custom circuit design, a key requirement is the capability to define and execute integrated Analog/Mixed-Signal (AMS) solutions by combining circuit/analog and digital/RTL design techniques to enable more efficient architecture, improved performance, and faster project execution.
• Exposure to AI-Enabled, and Agentic AI technologies, with the ability to adopt a "Design + AI" approach by leveraging innovative AI-driven solutions to accelerate design and validation, improve productivity, and enhance engineering effectiveness and performance.
• Design-Technology Co-Optimization (DTCO) initiatives by bridging process technology, device modeling, circuit design, and architecture exploration to optimize performance, power, area, and cost (PPAC), while collaborating across Technology Development, Design, Reliability, and Product teams to enable future memory-node pathfinding and product success.
• Deep knowledge of high-speed digital, analog, and mixed-signal circuit design, including power delivery circuits such as Bandgap References, LDOs, Bias Circuits, and the ability to develop block-level specifications based on system and link-budget requirements.
• Strong understanding of CMOS device physics, deep-submicron design challenges, power consumption trade-offs, mismatch analysis, Monte Carlo methodologies, transistor-level noise analysis, and circuit reliability considerations.
• Experience supervising complex analog layouts, defining IP floorplans, and driving parasitic-aware design methodologies through layout signoff.
• Proficiency with industry-standard EDA tools and design flows, including Cadence ADE/Virtuoso, Spectre, AMS Verification, EM/IR analysis, MATLAB, Calibre, and mixed-signal verification environments.
• Working knowledge of mixed-mode simulation, signal integrity, package interactions, ESD design, and system-level validation methodologies.
• Knowledge of digital design methodologies using RTL, with the ability to develop behavioral and system-level models using Verilog-A, Verilog/SystemVerilog, and Python.
• Strong communication, technical leadership, and cross-functional collaboration skills, with the ability to build effective working relationships and deliver results in a fast-paced, dynamic engineering environment.
• Self-motivated, self-directed, innovative, and capable of driving complex technical initiatives independently while contributing effectively as a team player.
• M.Tech. or Ph.D. in Microelectronics, or a related discipline, with 5+ years of semiconductor industry experience in analog/mixed-signal, high-speed interface, memory, SerDes, or AMS architecture design.

Job Profile(s):

Semiconductor Design Engineer 4

Relocation level: (TBD)

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