SoC Static Timing Analysis (STA) Engineer, HBM

Req ID:

JR106632 SoC Static Timing Analysis (STA) Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Static Timing Analysis (STA) Engineer, you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation HBM products. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing

integrity and drive timing closure across all modes and corners from initial design through tape-out. You will also lead the effort to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

This is a hands-on senior technical role for someone passionate about chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation.

Key Responsibilities will include, but are not limited to:

• Drive development of AI-hardware for next-gen LLM workloads, applying knowledge of gen-AI to drive AI-enabled timing closure methods.
• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions.
• Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, engineering change orders (ECOs), and close
• collaboration with physical design on placement, clock tree synthesis, and routing.
• Perform multi-mode, multi-corner (MMMC) analysis including clock domain crossing timing, on-chip variation (OCV, AOCV, POCV), and advanced-node timing methodologies.
• Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and partner with physical design teams on mitigation strategies.
• Build and maintain static timing analysis automation and flows using Python and Tcl for reporting, regression tracking, quality of results dashboards, and sign-off readiness.
• Conduct post-silicon timing correlation and develop organization-wide static timing analysis methods. Define sign-off standards, timing closure guidelines, readiness reviews, and tape-out sign-off gates. Communicate timing status, risks, and closure plans clearly to design leads and senior management.

Minimum Qualifications:

• 15+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below.
• Deep expertise with industry-standard static timing analysis tools such as Synopsys PrimeTime and/or Cadence Tempus.
• Expert understanding of advanced timing concepts including multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing.
• Proven ability to develop and manage complex hierarchical SDC constraints for large systems on chip with multiple clock and power domains.
• Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.

Preferred Qualifications:

• Experience with high-bandwidth memory (HBM), dynamic random-access memory (DRAM), or memory-centric system-on-chip designs.
• Exposure to design for test timing, including scan, memory built-in self-test (MBIST), and Joint Test Action Group (JTAG) interfaces.
• Experience with chiplet-based or three-dimensional integrated circuit designs and die-to-die interface timing methodologies.

Job Profile(s):

Machine Learning Engineering MTS

Relocation Level: TBD

Before Getting Started

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The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$199,000.00 - $347,000.00 a year

Additional compensation may include benefits, bonuses and equity.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

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