Sr. Manager - SOC Verification

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

As the SoC Verification Manager, you will be a critical leader in our dsPIC Microcontroller Business Unit, responsible for ensuring the functional integrity of our next-generation 32-bit MCU products. You will lead, mentor, and scale a high-performing team of 20+ verification engineers to execute complex verification strategies for SoCs featuring ARM and specialized proprietary cores.

Your mission is to drive "First-Pass Silicon Success" by bridging the gap between architectural intent and silicon implementation through cutting-edge UVM and Formal methodologies.

Key Responsibilities

• Strategic Leadership: Own the end-to-end verification strategy, from initial test plan development to final tape-out sign-off for multiple concurrent MCU projects.
• Team Management: Lead and develop a global team of 20+ engineers. Manage resource allocation, performance reviews, and technical career growth.
• Architecture Oversight: Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows.
• Technical Excellence: Drive the adoption of advanced techniques, including Formal Verification, Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
• Cross-Functional Collaboration: Partner closely with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve complex integration issues and architectural bottlenecks.
• Methodology Innovation: Continuously improve verification efficiency through automation, Python/Perl scripting, and the integration of AI-driven verification tools.

Requirements/Qualifications:

• Education: Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
• Experience: 12+ years in SoC Verification, with at least 5 years in a formal leadership or management role.
• Domain Expertise: Proven track record of successful tape-outs for 32-bit Microcontrollers. Deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules).
• Processor Knowledge: Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.
• Methodologies: 
  • Expert-level command of SystemVerilog and UVM (Universal Verification Methodology).
  • Strong hands-on experience with Formal Verification (Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
• Protocol Proficiency: In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
• Verification Infrastructure: Experience defining coverage-driven verification (CDV) metrics and managing massive regression suites. Module level verification plan development, TB plan, TB development and fullchip integration of the module level TB, develop effective functional assertions and coverpoints.

Preferred Skills

• Strong background in Gate-Level Simulations (GLS) and power-aware verification.
• Experience with Post-Silicon Validation, customer support and its alignment with pre-silicon test plans.
• Experience with analog mixed-mode (AMS) simulations.
• Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.

Travel Time:

0% - 25%

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.