Principal Engineer - Design for Test

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Job Description:

Microchip AES Design team in Bangalore is looking for an experienced and motivated Design-For-Test Principal Engineer to provide test
hardware solution for various microchip Business units. As a member of test development team, you will be responsible for understanding the
existing DFT test structures and clock strategy used across multiple business units and provide architectural improvements to improve test
coverage. The candidate should have experience with ATPG and MBIST. The candidate should have in depth knowledge of Tessent/Modus
tool execution.

Requirements/Qualifications:

Hands on expertise on handling DFT on hierarchical designs.

Hands on expertise on Tessent/Modus ATPG tool for DFT setup and pattern generations.

Hands on expertise on Tessent/Modus MBIST tool for MBIST hardware generation.

Hands on expertise on Tessent/Modus diagnosis tool for on-silicon debug.

Hands on expertise SCAN pattern simulations and debug.

ATPG with the pattern delivery to the test engineering team.

Sound knowledge of Scan Stitching, Scan Compression, MBIST & JTAG Techniques.

Should have good post silicon DFT bring-up and debug experience.

Should have a good knowledge of simulation debug and prior experience at SoC level.

Excellent written and verbal communication skills.

Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.

Experience:

Bachelors/Masters in Electronics or equivalent degree with 9+ years of experience

Travel Time:

0% - 25%

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