- Location
- Bangalore, India
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Experience
- 5+ years
- Education
- Master
- Source
- Workday
Description
Job Qualification
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, VLSI, or a related field.
- 5–7 years of experience in DFT, ASIC, or SoC design and test-related roles.
- Strong expertise in Scan, MBIST, LBIST, JTAG, Boundary Scan, and Test Compression methodologies.
- Hands-on experience with industry-standard DFT and ATPG tools such as Siemens Tessent, Synopsys TestMAX/TetraMAX, or Cadence Modus.
- Solid understanding of ATPG concepts, fault modeling, and defect coverage analysis, including stuck-at, transition, and path-delay faults.
- Strong background in SoC-level DFT architecture, implementation, and verification.
- Experience with RTL design and verification using Verilog and SystemVerilog.
- Good understanding of low-power DFT methodologies and UPF/CPF-based design flows.
- Experience with scan chain optimization, test point insertion, and DFT timing closure.
- Familiarity with physical design constraints and DFT-aware implementation flows.
- Experience supporting silicon bring-up, ATE debug, and production test qualification.
- Exposure to mixed-signal DFT, memory test, and high-speed interface testing is highly desirable.
Job Responsibility
- Define and implement SoC DFT architecture, including Scan, MBIST, LBIST, JTAG, Boundary Scan, and Test Compression.
- Drive end-to-end DFT implementation from architecture definition through RTL integration, synthesis, and silicon bring-up.
- Develop and validate scan insertion, scan chain stitching, test point insertion, and ATPG pattern generation to achieve target fault coverage.
- Perform RTL and gate-level DFT verification, debug DFT issues, and ensure design testability requirements are met.
- Implement and optimize Memory BIST (MBIST) and Logic BIST (LBIST) solutions for complex SoCs.
- Collaborate with RTL Design, Physical Design, Verification, Product Engineering, and Test Engineering teams to ensure successful DFT integration and timing closure.
- Support ATPG pattern validation, ATE bring-up, silicon debug, and production test activities.
- Optimize test coverage, pattern count, test power, and test execution time to meet product quality goals.
- Develop and maintain DFT architecture specifications, verification plans, and technical documentation.
- Drive continuous improvement of DFT methodologies, automation flows, and best practices across projects.
- Strong analytical, debugging, and problem-solving skills with the ability to drive complex technical issues to closure.
- Excellent communication and collaboration skills, with experience working across global multi-functional teams.
