Chip Lead

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments.

The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line.

What You Can Expect

Job Responsibilities
As a Chip Lead, you will be responsible for driving a complete chip/chiplet program, taking technical ownership of the entire scope. Your role will encompass contributing to architecture definition, design, verification, DFT, implementation & sign-off.
Responsibilities:
- Leading the program end-to-end from architecture to tapeout.
- Work with systems teams to define architecture and design specifications.
- Work with Design teams to define micro-architecture/ design implementation (module level & SOC level).
- Ensure compliance to the company’s design process/ design flows. Ensure design maturity at intermediate milestones, maintaining schedule cognizance, and adhering to defined quality metrics throughout the development process.
- Overseeing the development of RTL code and ensuring its correctness.
- Reviewing the verification process & verification scope/plan, including functional, coverage-driven, and power-aware verification.
- Reviewing the Emulation plan/ scope to help define Tape-out gating items
- Coordinating with DFT & Physical design teams to ensure successful implementation and tape-out.
- Conducting reviews for performance tests to evaluate system stability, scalability, and reliability.
- Addressing the complexity of multi-die solutions, including inter-die communication, power management, and thermal challenges.
- Designing and implementing chips targeting datacenter applications, focusing on high performance, low power consumption, and scalability.
- Collaborating with cross-functional teams across sites for smooth execution of the program, including post-Si debugs
- Providing technical guidance and mentorship to junior engineers.
- Ensuring compliance with industry standards and best practices

What We're Looking For

- Bachelor's or Master's degree in Electrical or Computer Science Engineering or a related field.
- 16+ years of technical experience with 5+ tapeouts as a Chip lead.
- Proven experience in leading RTL2GDSII programs.
- Strong background in RTL design, verification methodologies, and physical design.
- Proficiency in scripting languages (PERL/Python) and EDA tools.
- Solid understanding of system and processor architecture, advanced memory, and IO technologies.
- Experience with multi-die solutions and addressing their associated complexities.
- Knowledge of designing chips for datacenter applications, including performance optimization and power management.
- Excellent self-motivation, communication, problem-solving, and teamwork skills.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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