Job Details:

Job Description:

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.

Join us in our journey to becoming the world's #1 FPGA company!

Altera is searching for a Product Development Engineer to join our Manufacturing Content Development Engineering Group!

The Manufacturing Content Development Engineering Group is responsible for architecting, developing, validating and productizing high quality manufacturing test content for FPGAs to screen out any manufacturing defects and thus guaranteeing the highest quality of outgoing parts to customers.

Other responsibilities of the Product Development Engineer include but are not limited to:

• Develop and implement DFT strategies for FPGAs, including scan insertion, BIST (Built-In Self-Test), and test compression techniques.
• Collaborate with RTL design and verification teams to ensure testability features are embedded efficiently.
• Define and implement test plans, patterns, and fault models to ensure optimal test coverage and yield.
• Develop and maintain MBIST manufacturing test content flows and scripts.
• Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out.
• Analyze test results, debug silicon failures, and provide root cause analysis.
• Work with manufacturing and test teams to optimize test time, cost, and quality.
• Analyze early customer returns with emphasis on driving test hole closure activities.
• Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations.
• Stay updated with industry trends and emerging DFT/test technologies.

Salary Range 

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.  

 

$106,200 - $153,675 USD 

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. 

#LI-MD1

Qualifications:

Minimum Required Qualifications:

Bachelor's or Master's Degree in Electrical Engineering or related field, with 3+ years of industry experience in the following:

• Experience in IC design and IC test.
• Experience in DFT methodologies such as scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG and JTAG networks
• Test development tools (e.g., TessentIJTAG, Tessent MemoryBIST, FastScan, Tessent Shell etc).
• Experience with RTL design, synthesis, and verification flows.
• Experience with fault grading, test time analysis, test coverage analysis, and test yield enhancement.
• Scripting skills in Python, Perl, TCL, or similar.
• Semiconductor manufacturing test processes.
• Digital and analog circuit fundamentals.

Preferred Qualifications:

• Master's Degree in Electrical Engineering, or equivalent (or other related Engineering degree).
• Experience with Tessent MBIST flows for pattern development and knowledge of memory repair schemes and Memory algorithms is a plus.
• Post-silicon experience including pattern conversion, Automated Test Equipment (ATE) pattern bring-up and silicon characterization is a plus.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.