Principal Digital Design Engineer

Principal Digital Design Engineer

About Astera Labs

Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.

As AI workloads continue to scale, Astera Labs is developing innovative connectivity products that deliver industry-leading performance, reliability, and scalability. We are looking for an experienced Digital Design Engineer to join our Silicon Engineering team and help architect and build the next generation of connectivity solutions.

Position Summary

We are seeking a Principal Digital Design Engineer with deep expertise in RTL design, microarchitecture, and high-performance SoC development. In this role, you will lead the architecture and implementation of complex digital subsystems for cutting-edge AI infrastructure products.

You will collaborate closely with Architecture, Verification, Physical Design, Firmware, Validation, and Product Engineering teams to deliver high-quality silicon while driving technical excellence across multiple programs.

Key Responsibilities

Architecture & Design

• Drive the microarchitecture and RTL implementation of complex digital IPs and SoC subsystems.
• Translate architectural specifications into efficient, high-quality RTL designs.
• Define scalable and reusable architectures for high-performance silicon products.
• Optimize designs for performance, power, area (PPA), reliability, and testability.
• Participate in architecture reviews and influence key technical decisions.

RTL Development

• Design and implement synthesizable RTL using Verilog/SystemVerilog.
• Develop high-speed datapaths, control logic, arbitration schemes, finite state machines, and protocol engines.
• Ensure RTL quality through comprehensive design reviews, linting, CDC/RDC analysis, and synthesis validation.
• Support design closure throughout the development lifecycle.

Protocol & Connectivity Design

Lead or contribute to the design of IPs supporting:

• Compute Express Link (CXL)
• PCI Express (PCIe Gen4/Gen5/Gen6)
• Ethernet (10G–800G)
• High-speed SerDes interfaces
• AXI, APB, and AHB interconnects
• Memory subsystems and coherent interconnects

Cross-Functional Collaboration

• Partner with Verification teams to ensure comprehensive functional coverage and rapid issue resolution.
• Collaborate with Physical Design teams to achieve timing closure and implementation goals.
• Work closely with Firmware, Validation, and System Engineering teams during silicon bring-up and product qualification.
• Support post-silicon debugging and customer issue resolution as required.

Technical Leadership

• Provide technical leadership across multiple design programs.
• Mentor engineers through design reviews, architecture discussions, and technical coaching.
• Drive continuous improvements in RTL quality, design methodologies, and engineering productivity.
• Contribute to IP reuse, coding standards, and design best practices across the organization.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Principal Engineer: minimum 10+ years of experience in digital design.
• Senior Principal Engineer: minimum 15+ years of experience in digital design with demonstrated technical leadership.
• Strong expertise in Verilog/SystemVerilog RTL development.
• Proven experience delivering multiple successful silicon tape-outs.
• Strong understanding of digital logic design, computer architecture, and SoC integration.
• Experience working with synthesis, lint, CDC/RDC, STA, and design sign-off flows.
• Excellent debugging and analytical skills.

Preferred Technical Skills

Experience in one or more of the following:

• Compute Express Link (CXL)
• PCI Express
• Ethernet MAC/PCS/PMA
• High-speed networking or connectivity IP
• Cache coherency protocols
• AI accelerator or data center SoCs
• Packet processing architectures
• DMA engines
• Memory controllers
• High-speed interconnects
• Design for Test (DFT)
• Low-power design techniques

Tools & Methodologies

• Verilog/SystemVerilog
• Synopsys Design Compiler
• Cadence Genus
• SpyGlass or equivalent lint/CDC tools
• Static Timing Analysis (STA)
• Git or similar version control systems
• Python, Tcl, Perl, or Shell scripting

Preferred Experience

• Experience designing semiconductor products for AI infrastructure, cloud computing, networking, or storage applications.
• Proven ability to lead complex design initiatives from architecture through silicon bring-up.
• Familiarity with chiplet architectures, heterogeneous compute systems, and high-speed interconnect technologies.
• Strong track record of solving complex design challenges and delivering innovative solutions.