ISP Design Engineer, up to Staff

Architect, design, and optimize ISP hardware modules including demosaic, noise reduction, color correction, tone mapping, sharpening, HDR merging, spatial/temporal filtering, and other image quality pipelines. Translate imaging specifications and algorithm requirements into efficient micro architecture and hardware friendly implementations, balancing image quality with area, power, and latency constraints. Develop C/C++/SystemC models for algorithm validation, performance estimation, bandwidth analysis, and design space exploration. Evaluate ISP performance using KPIs such as image quality metrics, throughput, latency, memory bandwidth, and power efficiency; propose design enhancements based on quantitative data. Collaborate with verification teams to define test plans, reference model comparisons, coverage metrics, and debugging flows for robust pre silicon validation. Work with PD teams to meet PPA targets via pipeline design, timing closure strategies, clock/power domain planning, and architecture trade off analyses. Support post silicon bring up, tuning, debugging, and performance correlation against pre silicon models. Contribute to architecture documentation, programming guides, and cross team design reviews. Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. Solid understanding of image signal processing algorithms and concepts (demosaic, filtering, HDR, color pipelines, noise reduction, etc.). Strong RTL design skills (Verilog/SystemVerilog) and experience in micro architecture development and datapath design. Proficiency in C/C++/SystemC/Python for modeling, simulation, and algorithm analysis. Experience with SoC integration, memory hierarchy, bandwidth/performance estimation, and low power design techniques. Ability to work cross functionally and deliver designs from concept to silicon. Experience implementing ISP pipelines or image quality algorithms in hardware as seen in roles such as Camera Engineer、Camera Senior Engineer 或 Camera Staff Engineer Background in computational photography, multi frame fusion、CV workloads、or ML based IQ algorithms。 Familiarity with sensor pipelines、3A（AWB/AEC/AF）、tuning workflows、or camera system integration。 Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.