Senior Analog Layout Design Engineer

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre Do you love the challenge of crafting the securest silicon possible? If so, we want to hear from you. Come, join our ASIC Security team and help build the real-time, cost-effective computing platform driving our success across several exciting and quickly growing fields.