- Location
- Bengaluru, KA,IN, IN
- Type
- Full-time
- Department
- Engineering
- Education
- PhD
- Source
- Eightfold
Description
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. BA/BS degree in CS/EE/ECE with 7+ years' experience. 5+ Experience in Emulation platforms - Palladium, Zebu, Veloce, FPGAs Skilled in assembly, C/C++ language embedded firmware. Proficient in debug tools , waveform analysis, trace signals and debug issues in RTL(Register Transfer Level). Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Excellent problem-solving and cross-team collaboration skills. Good understanding of micro-processor architecture, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of SoC architecture and subsystem integration. Experience with pre-silicon validation flows and post-silicon debug correlation. Strong communication skills to articulate complex technical issues to diverse stakeholders Understand the IP arch, micro arch features and work with validation team for execution on emulation platforms. Reproduce, analyze and support in debug of complex out of order CPU pipeline issues. Collaborate with CPU Design, verification, validation teams to reproduce the Silicon, HW fails on emulation platforms and debug. Develop validation methodology and test contents to exercise on emulators during pre-Si phase. Work with emulation team to suggest architecture enhancements for improved debug capabilities. Work with SOC bring up teams, software teams and support in end-to-end bring-up of CPU in pre-Si phase. Provide technical guidance and mentorship to junior engineers in the validation/debug domain.