HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff (US Citizenship Required)

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 4+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low-power design techniques, including clock gating and multi-voltage domains. Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies. Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling. Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe). Understanding of package-level clock planning and signal integrity. Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2). Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing, congestion, and DRC issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support physical verification including DRC, LVS, and antenna checks. Work closely with backend teams for tapeout preparation and signoff. Excellent scripting skills (TCL, Python, Perl) for reference flow automation. Execute full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry-standard tools (e.g., Calibre, Pegasus, ICV). Customize and optimize reference physical verification flows to align with project needs and foundry requirements. Perform GDS-to-GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness. Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi-corner/multi-mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross-domain timing and false/multicycle path handling. Participate in design reviews, providing insights on timing risks and mitigation strategies. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Collaborate with RTL, synthesis, and physical design teams to integrate power-aware features such as power gating, retention, isolation, and level shifting. Perform power-aware static checks, simulation, and formal verification to validate power intent. Support signoff verification including power-aware LVS/DRC, STA, and EM/IR analysis. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low-power guidelines and contribute to successful tapeout. Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages. Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects. Works independently with minimal supervision.