- Location
- Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Source
- Eightfold
Description
Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Take part in floor planning, custom layout and verifying against design rules and schematics. Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
Skills
.NETSalesforce
