- Location
- Hybrid Remote/SF Bay Area/Austin/Boston
- Workplace
- Hybrid, Remote
- Department
- ASIC
- Source
- Greenhouse
Description
What We’re Looking For:
We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.
Ideal Background:
An ideal candidate will have:
- Experience with full ownership of the specs and drove implementation for at least one SoC/die
- A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs
- Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks
Nice to Have:
- Experience with multi-die/multi-chiplet/MCM designs
- Experience with reticle-max/large-die SoC architecture
- Understanding of levers available for improving PPA
- Track record of very high speed A0 silicon delivery