Senior/Staff NAND Design Rule Engineer

Req. ID:

JR113413 Senior/Staff NAND Design Rule Engineer (Evergreen)

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

As a Senior/ Staff NAND Design Rule Engineer in Process Integration (Storage Technology Group), your primary role is to drive and contribute to next generation 3D NAND development efforts. You will be working with several peer groups to define, execute, and coordinate effective actions to enable multiple projects to hit key achievements and timelines

Responsibilities include but are not limited to the following:

• Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp.

• Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate.

• Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations).

• Develop automated solutions and agentic capabilities to ensure sufficient design rule coverage, accuracy and consistency with other technology collaterals.

• Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data

• Support design rule checking (DRC) of both base and mask layers and interface with physical verification team.

• Define algorithms for generation of mask data from drawn base layer data.

• Involve projects across multi-disciplinary teams focusing on layout and mask generation issues

Qualifications and Experience

• "Master’s or PhD degree with at least 3 years of experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development."

• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge.

• Proven ability to develop code and agentic solutions using Python or other industry standard programming languages or tools such as Claudecode.

• Exposure to design, design rule & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is required.

• Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle.

• Strong knowledge of advanced semiconductor process flow, the scaling issues of memory (non-volatile/volatile memory technologies) from device and product perspectives, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, and CMOS under array.

• Strong communication skills (written, verbal and presentation).

Job Profile(s):

Semiconductor Design Engineer 3

Relocation level: (TBD)

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