SoC RTL Design- Staff Engineer

Experience in Logic design /micro-architecture / RTL coding is a must. Experience in Verilog/System-Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 10-15 years of experience in digital front-end ASIC/RTL design. Work closely with the SoC verification and validation teams for pre/post Silicon debug