- Location
- China, Shanghai
- Type
- Full-time
- Department
- Engineering
- Education
- PhD
- Source
- Workday
Description
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.
What You’ll Be Doing:
Develop timing analysis and timing closure methodologies, and implement flow automation for large-scale, high-speed semicustom chips based on deep submicron processes.
Establish methodologies for timing constraints and SDC (release, including automatic constraint generation, constraint linting, and validation of timing exceptions.
Take responsibility for EDA tool evaluation and collaborate with EDA vendors to enhance commercial timing signoff tools, constraint lint tools and spice simulation tools.
Develop and validate flows for PT-spice regression, silicon correlation for high-speed designs.
Develop flows/recommendations on STA and PNR in deep submicron physical effects aging, IR drop, crosstalk, noise and etc.
Develop flows and methodologies to improve design performance, predictability, and silicon reliability.
What We Need To See:
Master’s or PhD degree in Electrical Engineering or Computer Engineering, with 2+ years of hands-on experience in physical design implementation.
Proven experience in synthesis, timing constraints definition, timing analysis, and timing closure.
Advanced proficiency in commercial STA tools, such as Synopsys PrimeTime, Spice, Redhawk, Cadence Tempus, Synopsys TCM, or Ausdia TimeVision.
Solid expertise in STA principles and timing signoff processes including good knowledge of crosstalk analysis, IR-drop, electro-migration, noise, OCV, timing margins.
Hands-on experience in advanced CMOS technologies, design with FinFET technology 7nm/5nm/3nm and beyond.
Proficiency in at least one programming/scripting language, including Perl, TCL, Python, or C++.
Strong verbal and written communication skills, with the ability to collaborate effectively in cross-functional teams.
Ways To Stand Out From The Crowd:
Experience in flow development or automation for ASIC backend design.
