Senior Engineer Verification

Your Role

Key responsibilities in your new role

• Take responsibility of developing SV RNM models and its verification against schematic.
• Developing automatic checkers
• Gain knowledge on AMS methodologies/Simulators
• Take responsibility of analog vectors (test parameters) verification at SoC level using DMS verification flow involving UVM testbench and RNM models.
• Knowledge on Scripting.

Your Profile

Qualifications and skills to help you succeed

• Mixed signal verification engineers responsible for AMS verification of Multi phase controllers, power switches.
• Development of SV RNM models for analog blocks like ADC, buck-boost controller, ldo etc.
• Verification of SV RNM models against schematic.
• Verification of analog vectors at SoC (DMS verification flow involving UVM, SV RNM)
• Good understanding on EDA tools/simulators (Cadence - virtuoso schematic editor, Xcelium,APS/XPS).
• Good understanding of analog design concepts
• Automation using shell/Perl/Python script.
• Self-motivated to work effectively & should be able to handle work independently.

Contact:

[email protected]

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