Hiring.Camp

SerDes Micro Architect

Apple

Source
Custom

Skills

Compliance

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30

Lead Analog SerDes Architect/Design Engineer

Intel·USA - CA - Santa Clara, US·Hybrid

8mo ago

Lead Analog SerDes Architect/Design Engineer

Intel·USA - CA - Santa Clara, US·Hybrid

8mo ago

Senior SerDes Architect and Lead

Omni Design Technologies·Milpitas +4·Hybrid

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Senior Serdes System Design Engineer/Architect

Broadcom·USA-TX-Austin - River Place B7, US +2

4w ago

Senior Serdes System Design Engineer/Architect

Broadcom·USA-TX-Austin - River Place B7, US +2

1mo ago

Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes

Omni Design Technologies·Milpitas·Onsite

2mo ago

Senior High Speed SerDes Validation Engineer

Nvidia·Santa Clara, CA

1d ago

Senior High Speed SerDes Validation Engineer

Nvidia·Santa Clara, CA

1d ago

Principal AE, Serdes Design IP

Cadence Design·SAN JOSE 10, US

5d ago

 Principal AE, Serdes Design IP

Cadence Design·SAN JOSE 10, US

5d ago

Design Verification Tech Lead- SerDes/PHY IP

Asteralabs·San Jose, California +1

1w ago

Serdes Characterization & Post-Silicon Validation Engineer

K2Spacecorporation·Seattle, WA +1

1w ago

Serdes Characterization & Post-Silicon Validation Engineer

K2Spacecorporation·Los Angeles, CA

1w ago

Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland

Qualcomm·Cork, CO

1w ago

Principal Product Engineer – High-Speed IP SerDes

Cadence Design·GYEONGGI-DO 03, Korea

2w ago

Firmware Engineer – SerDes PHY (all levels)

Qualcomm·Toronto, ON

3w ago

Serdes PHY Analog Design Engineer

Qualcomm·Bengaluru, KA

3w ago

Software Engineer – High-Speed SerDes

Eridu Ai·Saratoga, CA

3w ago

Principal Design Verification Engineer- SerDes/PHY IP

Asteralabs·San Jose, California +1

4w ago

Senior SERDES Layout Engineer

Qualcomm·Noida, UP

1mo ago

Transmitter (Tx) SerDes Design Lead - 224G/448G

Ciena·Canada- Ottawa- 383 Terry Fox- Bldg C

1mo ago

SerDes High Speed IP ATE Test Development & Characterization Engineer

Qualcomm·Singapore, SG

1mo ago

Staff Analog Design Engineer, SerDes Clocking

D Matrix·Santa Clara·Hybrid

1mo ago

Principal Analog IC Design Engineer, High Speed SerDes

Cadence Design·SAN JOSE 08, US

1mo ago

Signal Integrity Engineer - Serdes, Satellites (Starlink)

Spacex·Palo Alto, CA

1mo ago

Signal Integrity Engineer - Serdes, Satellites (Starlink)

Spacex·Redmond, WA +1

1mo ago

Head of Program & Portfolio Management – SerDes Networking Solutions

Job Listings·San Jose, US

2mo ago

SerDes Application Engineer

Broadcom·USA-CA San Jose Innovation Drive, US

2mo ago

Sr. SI/PI Engineer - Serdes, Satellites (Starlink)

Spacex·Palo Alto, CA

2mo ago

HPC High-Speed SerDes Interface Evaluation Leader

Renesas Electronics·Kodaira, Japan·hybrid

3mo ago