Design Engineer (Low Power)

Experience in SoC low power micro-architecture, low power design and methodology, Power Intent/Implementation, power estimates, power analysis tools and power reduction techniques is a must. Experience in ARM IP based full chip debug is preferred. Experience in silicon bring up and debug is a must Experience in ARM IP based full chip debug is preferred Experience in PCIE/USB peripherals is preferred Experience in CPU sub system-based design is preferred Experience in low power design from project start to volume chip production for at least one product cycle is preferred Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.