SR ENGINEER, DPG GRAPHICS VERIF

Participate in simulating, analyzing, and debugging pre-silicon full chip designs by applying leading edge verification technique Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Analytical capability for complex gate level circuit designs Basic understanding of CMOS circuit designs Familiar with both SPICE and Verilog simulations Good communication skills and ability to work well in a team