ASIC Verification Principal Engineer

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Company:

Qualcomm China

## Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Requirements:

Deep expertise in ASIC development, especially switch verification using System Verilog / UVM, SVA and Coverage-driven methodology, Emulation / FPGA validation

Deep expertise in Packet Forwarding switch architecture, including:

Forwarding pipelines (L2/L3, ACLs, tunneling)

Traffic management (QoS, scheduling, shaping)

Strong leadership and cross-functional influence capability

Strong debugging and system-level problem-solving skills

Excellent teamwork, interpersonal and communication skills.

Fluent in Chinese and English both verbal and written.

Ability to work in stressful situations with tight schedules to meet.

Description of Function & Responsibility

Define verification architecture for Packet Forwarding switch ASICs from Module level, Subsystem level to System level

Drive cross-functional alignment with HW, SW, and Product teams on networking features and performance verification

Drive schedule alignment and ensure on-schedule execution with Arch and Design Team

Mentor senior technical leaders and influence organization-wide engineering direction

Education:

MS in EE.

Experience:

15 to 20+ years ASIC design/verification experience. Experience in merchant silicon or Packet Forwarding ASIC is highly desirable.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

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