- Location
- Santa Clara, CA,US, US · Austin, TX,US, US
- Type
- Full-time
- Department
- Engineering
- Education
- PhD
- Source
- Eightfold
Description
Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate, and release flows and methodologies for floorplanning(power planning, pin placement) or PDV analysis(drc/lvs/antenna) Architect, maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency (Python and Tcl). Knowledge of data structures and algorithms Experience with automation Strong user of PNR tool Innovus or PDV Calibre tool or equivalent Experience with a broad variety of other Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
