- Location
- ZHUBEI 01, Taiwan
- Type
- Full-time
- Department
- Engineering
- Seniority
- Senior
- Experience
- 4+ years
- Education
- PhD
- Closing date
- Today
- Source
- Workday
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.
What you will do:
Improve the performance and correctness of UPF waveform generation across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
Improve SAGE-based UPF debug with Verisium for better performance and usability.
Help develop AI-assisted, Verisium-integrated UPF debug tools that reduce time-to-root-cause for low-power design issues.
Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
Help consolidate and unify UPF debug across Palladium and Protium.
What we are looking for
BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
equivalent), with critical evaluation of AI output.Strong debugging skills — root-cause analysis from logs, waveforms, traces, testcases, and user reports.
Ability to read, review, and reason about C++ code and object-oriented designs.
Scripting experience in Perl, Tcl/Tk, and/or Python.
Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
