- Location
- Santa Clara, CA,US, US
- Type
- Full-time
- Department
- Engineering
- Education
- Master
- Source
- Eightfold
Description
Work with CPU and SOC Architects to understand the concepts and high-level system requirements. Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture. Develop Verification Methodology, ensuring scalability and portability across environments. Develop Verification environment, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage. Develop Verification Plans and Testbenches for your functional domain. Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures. Track and report DV progress using a variety of metrics, including Bugs and Coverage. Deep knowledge of Micro-Processor Verification functions and Architectures, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in leading a small team of Verification engineers performing CPU Verification. Advance techniques such as: Formal, Assertions, and Silicon bringup, is helpful. In-depth knowledge of Micro-processor functions, Architectures, and Micro-architectures. Experience in writing Test plans, portable Testbenches, Transactors, and Assembly code. Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification. Ability to develop and work independently on a Block/Unit of the design. A minimum of BS degree in any of: {Computer Engineering, Electrical Engineering or Computer Science}.