- Location
- ZHUBEI 01, Taiwan
- Type
- Full-time
- Department
- Engineering
- Seniority
- Lead
- Source
- Workday
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Description:
• To provide key technical support in digital IC design implementation product demonstration, and sales presentations.
• To demonstrate strong ability and to be hands-on in full APR flow including floorplan, placement, timing analysis, CTS, signoff timing and PV closure methodology.
• To support key customer engagements on the business increase.
• Have real design tape-out experience especially (nice to have) for advanced node design.
• To play a leading role among other team members, while receive little instruction on routine and general assignments
Position Requirements:
• Master better with 3+ years working experience or Bachelor better with 5+ years’ experience in IC design. (Cadence Innovus experience will be a plus)
• Familiar with full APR flow including both logical + physical related (timing, SI , congestion , routing drc , hier design ....etc .) and MSV knowledge + methodology.
• Good communication in English and Chinese, good confidence and good attitude and self-motivation .
• Be familiar with shell/perl/tcl etc. script language.