Principal Engineer, Design For Test

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Principal Engineer, Design For Test at Marvell, you'll be a recognized DFT technical authority within the Custom Silicon Engineering team — a leader in large multi-die designs driving high compute performance and acceleration in custom AI and XPU markets. The role is challenging and requires an experienced DFT engineer who can work with existing solutions while creating new methodologies to address industry-first test challenges on the most advanced process nodes.

What You Can Expect

• Architect, lead, and implement DFT/Test on complex IP and SoC for multiple custom/compute/XPU ASIC/SoC designs across 3nm, 2nm, and emerging process nodes.
• Drive DFT architecture definition and own implementation of DFT/DFX features including scan, MBIST/BIRA/BISR, IJTAG, OCC, EDT compression, ATPG (SAF/TDF/NPSF), and post-silicon bring-up.
• Lead DFT execution from RTL through mass production readiness (MPR): insertion, validation, STA, pattern generation, ATE handoff, and silicon debug.
• Define and enhance DFT methodologies and tool flows; benchmark new approaches and enable next-generation methodology in the M1DPx Tessent-based environment.
• Mentor and guide a team of Staff and Senior Staff DFT engineers, enabling them to scale across multiple concurrent designs.
• Collaborate closely with Physical Design, timing closure, and product engineering teams on DFT physical implementation, scan chain optimization, and test data volume management.
• Interface with customers, design centers, and product engineering in DFT consultations, technical education, and design reviews for custom ASIC programs.
• Drive DFT automation and scripting improvements to improve first-time-right quality and reduce DFT cycle time.
• Support post-silicon bring-up, ATE failure debug, hardware diagnosis, and DPPM improvement initiatives for mass production.

What We're Looking For

• Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related field with 12+ years of experience; 10+ years of direct DFT experience in the custom chip design industry.
• Hands-on expertise across full DFT execution stack: Scan/MBIST/Validation/STA/IP-DFX/ATPG/Post-Silicon Bring-up and Debug.
• Thorough knowledge of DFT/Test architecture solutions; must have led DFT architecture definition on at least 2 designs.
• Strong experience with Siemens Tessent (preferred) or Synopsys TestMax for DFT insertion, ATPG, and MBIST flows.
• Experience with RTL and gate-level DFT flows for advanced ASIC designs.
• Understanding of physical design constraints, scan chain optimization, timing closure for DFT test modes (OCC/at-speed test).
• Demonstrated prior experience leading DFT on complex ASIC SoC tape-outs.
• Strong communication skills for customer-facing and cross-functional technical discussions.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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