Staff DFT Design Engineer, HBM

Responsibilities will include, but are not limited to: Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified. Collaborate with external partners and customers to align on custom DFT interfaces and security requirements when applicable. Support silicon bring‑up, debug, and qualification activities, including correlation between design intent and manufacturing test results. Bachelor's degree or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field. Strong fundamentals in digital design and DFT concepts (scan, MBIST, boundary scan, JTAG). Experience with RTL design (SystemVerilog/VHDL) and logic integration. Familiarity with semiconductor test flows from wafer probe through final test. 5+ years DRAM or ASIC DFT Design or Verification experience. Experience with HBM, DRAM, or advanced memory products. Knowledge of TSV‑based 3D integration and stacked‑die test challenges. Hands‑on experience with at‑speed test, compression, or advanced DFT methodologies. Exposure to DFT security, customer‑specific DFT interfaces, or custom test modes. Structured problem‑solving and debug perspective.