Principal Engineer, ASIC Physical Design

Req ID:

JR101100 Principal Engineer, ASIC Physical Design

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Summary

This position supports Micron’s DRAM Tester Solutions group, focusing on physical design implementation for processors, controller architectures, and ASICs. The role is responsible for full‑chip and block‑level physical design closure, low‑power implementation, timing, power, and signal integrity signoff, and successful tape‑out across advanced technology nodes.

Responsibilities:

• Lead block‑level and full‑chip physical design including floorplanning, placement, CTS, routing, and tape‑out.
• Drive timing closure across multiple modes and corners using industry‑standard STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full-chip closure work while coordinating with cross-functional teams.

Minimum Qualifications:

• Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Electronics, or Computer Architecture.
• Minimum of 15 years of hands‑on ASIC physical design implementation experience.
• Proven experience with multiple production tape‑outs in advanced process nodes.
• Strong expertise in low‑power design techniques including UPF/CPF and multi‑voltage systems.
• Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation.

Preferred Qualifications:

• Experience with Synopsys and Cadence physical design and timing tools.
• Hands‑on physical verification closure using Calibre and power integrity analysis tools.
• Experience with IR/EM signoff and resolution at block and full‑chip level.
• Background in memory tester designs, high‑speed interfaces, or microprocessor architectures.
• Experience developing and enabling APR flows for new technology nodes.

Job Profile(s):

ASIC Engineer 5

Relocation Level: TBD

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