MTS - HIG HBM - ARCHITECTURE

Req ID:

JR111358 MTS - HIG HBM - ARCHITECTURE

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry!

Position Overview:

We are searching for an HBM IO Design Architecture Engineer to build and own the end-to-end design quality system — including design checklist delivery, silicon data analysis, and cross-team data collection framework — ensuring that silicon learnings are systematically captured and fed back into the project before the next generation design is finalized.

The ideal candidate brings hands-on experience in design execution, simulation to silicon correlation, and cross-functional methodology development, and embraces AI-driven analysis and data-driven decision making to accelerate quality improvement cycles.

Responsibilities will include, but are not limited to:

• High-speed IO design architecture for HBM products

• Define and standardize IO design quality process from architecture to silicon

• Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis

• Contribute to cross group communication to work towards standardization and group success

• Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure the design quality

• Drive innovation into the future Memory generation with multifaceted work environment

• Leverage AI Assisted analytics to accelerate root cause identification from complex multi-variable silicon data

Successful candidates for this position will have:

• Prior industrial experience in high-speed clocking design at 32Gbps+ speed

• Good IO circuit design background with familiarity of both, analog and digital design and simulation experience required

• Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits

• Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc

• Good understanding on state-of-the-arts device characteristics and hands-on design experience

• Excellent problem-solving and analytical skills

• Strong documentation skills

• Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written

• Prior circuit debug experience through Product Engineering or equivalent preferred

• Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D, etc)

Required Experience

• MS or PhD in EE

• 10+ years of relevant Engineering or Design Engineering experience on high-speed IO, PLL, Tx, Rx, Equalization, clock tree

Job title and level can scale depending on experience and qualifications

Job Profile(s):

Systems Design Engineering MTS - Systems Design Engineering SMTS

Relocation Level: TBD

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