NPU / AI Processor RTL Design - Sr Staff

Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: Strong processor architecture knowledge Microarchitecture implementation Microprocessor integration Low power design Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 3+ years of Hardware Applications Engineering or Hardware Design experience or related work experience. OR Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 2+ years of Hardware Applications Engineering or Hardware Design experience or related work experience. OR PhD in Electrical/Electronics Engineering, Computer Engineering, or related field and 1+ year of Hardware Applications Engineering or Hardware Design experience or related work experience. simulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc. Develop RTL for multiple logic blocks of a DSP core Run various frontend tools to check for linting, clock domain crossing, synthesis, etc. Work with physical design team on design constrain and timing closure