High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)

Define and implement RTL architecture for SoC subsystems Integrate 3rd party IPs (USB, PCIe, UHS) into SoC designs and evaluate their performance Develop and optimize RTL code for performance, power, and area efficiency Collaborate with verification teams to ensure functional correctness and coverage Work with physical design teams to achieve timing closure and DFT compliance Debug and resolve RTL issues across simulation, emulation, and silicon validation Drive methodology improvements and automation for RTL design flow Provide guidance on coding styles, interface protocols, and best practices Occasional business travel across APAC and other regions may be required Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of hands-on experience in RTL design and SoC integration Proficiency in Verilog/SystemVerilog and RTL design methodologies Experience with integration and performance evaluation of USB / PCIe / UHS 3rd party IPs Familiarity with RTL-to-GDSII flow and timing closure Strong scripting skills in Python, Tcl, or Shell Excellent problem-solving and cross-functional communication skills Experience with low-power design techniques and clock/power domain crossing Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design Familiarity with post-silicon validation and debug of interface IPs Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools Comfortable working in a globally distributed engineering environment Experience correlating pre-silicon verification with post-silicon performance/yield Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.