Principal Engineer Position for System Power for Advanced 2.5D/3D High-Performance Compute

Develop and optimize PDN memory and computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W for mobile, compute, and XR applications Develop and validate models for power and power density modeling of multiple modules under different workloads Identify critical power scenarios and provide solutions within the constraints of packaging, floorplan, and PMIC module Develop PDN models in both time and frequency domain Simulate and emulate system power behavior on different power scenarios such as power-up, power-down, maximum performance, test/debug, and stand-by Identify locations of power switches and utilize optimal control mechanisms Floorplan 2.5/3D PDN under integration manufacturing constraints, testability, repairability, and high performance Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. Master's or Ph.D. in Electrical Engineering or a related field Experience in PDN, optimal decoupling capacitance placement, and power modeling Experience in modeling resonances on chips and 2.5D systems through resistance, inductance, and capacitance extraction Good knowledge of signal and power integrity, and chiplets Good knowledge of in the modeling of interconnects, uBumps, TSVs, and package Good knowledge of cross-power domain structures, clamping, and ESD protection schemes Good knowledge of PMIC architecture, design, and noise modeling Proficiency in use of EDA tools such as Voltus, Redhawk, SPICE, Virtuoso Experience in circuit and system design to model the power architecture Experience in memory architecture power assessment Experience in model order reduction of large RLC networks Familiar with memory architecture Ability to develop IBIS/Verilog-A/Modeling models of power modeling is strong plus Familiar in thermal modeling and hotspot mitigation Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) Familiar with high-frequency signal assessment