SENIOR ENGINEER HBM LAYOUT

Req ID:

JR115732 SENIOR ENGINEER HBM LAYOUT

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

## Job Description:

Join Micron Technology, Inc.’s HBM Team in Guadalajara, Mexico, and be part of a top-tier group of visionaries and scientists advancing High Bandwidth Memory (HBM) technologies. These technologies drive artificial intelligence and high-performance computing solutions. As a Senior Engineer HBM Layout, you will collaborate with international teams on multiple projects to ensure accurate execution and timely delivery of vital layouts.

## Responsibilities:

• Build and develop analog, mixed-signal, and custom digital blocks, along with full-chip level integration support.
• Perform layout verification tasks, including LVS/DRC/Antenna checks, quality control, and documentation.
• Ensure timely delivery of block-level layouts with outstanding quality.
• Lead planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and achievements.
• Communicate effectively with global engineering teams to determine project success.
• Apply and build AI-enabled methodologies for automation and problem-solving.

## Minimum Qualifications:

• 5+ years of experience in analog/custom layout development in advanced CMOS processes, spanning various technology nodes (Planar, FinFET).
• BE or MTech in Electronic/VLSI Engineering, or a related field.
• Proficiency in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is essential.
• Hands-on experience in crafting layouts for critical blocks such as Temperature Sensors, PLL, ADC, DAC, LDO, Bandgap, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.
• Strong knowledge of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, Coupling, Crosstalk, IR-drop, active and passive parasitic devices).
• Understanding of layout effects on circuit performance, including speed, capacitance, power, and area.
• Capability to comprehend build constraints and implement high-quality layouts.

## Preferred Qualifications:

• Experience supporting multiple tape-outs is highly advantageous.
• Proven track record in managing multiple layout projects while ensuring quality checks at all stages.
• Outstanding problem-solving skills in the physical verification of custom layouts.

Become involved in Micron’s exciting path to innovate and change how the world interacts with information to improve life!

Semiconductor Design Engineer 3

Relocation Level: TBD

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