HBM SOC Design Engineer

Analyze customer requirements and specification documents, work with IP vendors to select off-the-shelf IPs, and modify or custom design new ones if needed. Review architectural specifications and provide constructive feedback to help create high-quality specifications. Writing specifications, developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static checks Proactively identify and flag quality issues, performance problems, and opportunities to reduce power consumption in architecture, microarchitecture, RTL, or circuits. Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures. 3+ years of relevant job/skill-related experience. Proficiency in microarchitecture and high-quality RTL development with the ability to write and test code in System Verilog. Experience dealing with clock domain crossings (CDC), static timing analysis, synthesis design constraints, and closing timing by using logic techniques, false path constraints, and multi-cycle path constraints. Experience with SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc. Understanding of design for testability concepts such as MBIST and scan and how to write RTL for testability. BSEE or higher with a track record of innovation and problem-solving in high-performance and/or low power SOC development Familiarity with scripting languages such as Python Experience with working on one or more of the following IPs: UCIE, Memory Controller, NOCs. The ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds