- Location
- Markham, ON,CA, CA · Toronto, ON,CA, CA · Vancouver, BC,CA, CA
- Type
- Full-time
- Department
- Engineering
- Source
- Eightfold
Description
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Candidate will be responsible for design/developing next generation power control systems. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence.
Responsibilities
Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.
Skills/Experience Sr Engineer / Staff Engineer
5 to 8 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
Familiar with UPF and power domain crossing
Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus
Skills
Perl
