Job Details:

Job Description: 

Our Team:
Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact. 

The Role and Impact
As our SLT Test Lead, you will own the system-level test strategy and drive the hardware, DFT, and system definitions needed to support it. You will define the test plan in partnership with the validation teams - aligning on content, coverage and deliverables - and own the ATE-versus-SLT partitioning decision and the correlation between the two.

Key Responsibilities

• Develop, modify, and execute comprehensive test plans to ensure platform testability and manufacturability.
• Define test equipment, test case requirements, and write test content, standards, and procedures to achieve high test coverage.
• Drive the development of validation methodologies, execute validation plans, and debug failures to determine root causes and recommend corrective actions.
• Analyze test results to ensure platform functionality aligns with specifications and performance expectations.
• Modify test infrastructure design to support automated builds and test execution across various hardware platforms and operating systems.
• Collaborate with Architecture, Design, Verification, and Validation teams to improve test coverage and platform quality.
• Document test results, support debugging activities, and monitor yield, failure, and retest issues during builds.
• Work closely with the factory to address and resolve issues in a timely manner.
• Apply emulation and platform-level tools to improve validation processes and enhance platform lifecycle.

Qualifications:

• Bachelor's degree in a scientific field such as Electrical Engineering, Computer Engineering, Physics, Mathematics, Computer Science, or a related discipline.
• 6+ years of hands-on experience in platform validation, test engineering, or a related domain, including demonstrated expertise in systematic debugging and validation techniques
• Proficiency in tools and methodologies related to electrical validation, system-level testing, and test automation.
• Solid knowledge of electrical fundamentals and circuit testing principles
• Experience with test content development, data analysis, and data management for debugging purposes.
• Expertise in designing and executing test plans, including automated test execution.
• Strong problem-solving abilities and analytical skills, with the ability to recommend effective corrective actions
• Familiarity with yield monitoring, volume validation, and systems-level test methodologies
• Programming experience in C++, Python, Perl, or equivalent languages.

What will make you stand out

• Experience as a Technical Lead, SLT Lead or similar leadership role is an advantage.
• Practical implementation, experience and use of AI co-design environment
• Hands-on experience with test-house/OSAT production
• Emulation experience coupled with System Validation

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Israel)

Primary Location: 

Israel, Haifa

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*