Lead Layout Engineer

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Company:

Qualcomm India Private Limited

## Job Area:

Engineering Services Group, Engineering Services Group > Layout Engineer

General Summary:

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

OR

Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

OR

High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

*Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).

5+ years of expertise in high speed / Analog / Mixed signal layouts in lower nodes with Bachelor's in Electrical or Electronics Engineering or equivalent. Owning and delivering top‑level physical layout for complex analog, digital, or mixed‑signal designs across technology nodes.

Proficient in meeting layout performance, reliability, manufacturability, and quality requirements, adhering to foundry DRC/LVS and internal design guidelines. Proficient in Cadence Virtuoso layout XL / GXL / EXL and Calibre physical verification flow and expertise in debugging skills.

Ability to work & communicate effectively with global engineering teams. Effectively multitask and lead parallel projects, coordinating execution and priorities by well collaborating with the team members.

Capable of leveraging automation and having scripting expertise to eliminate repetitive manual tasks, improving efficiency and reducing total turnaround time. Act as a technical point of contact for layout‑related discussions with design, verification, CAD, and technology teams.

Identify risks early and proactively develop mitigation plans to ensure on‑time delivery of layout milestones.

Mentor junior layout engineers by reviewing work, sharing best practices, and promoting design quality and efficiency

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