- Location
- SRR4 - SRR4 - Sarjapur 4, India
- Type
- Full-time
- Department
- Engineering
- Seniority
- Lead
- Experience
- 20+ years
- Education
- PhD
- Source
- Workday
Description
Job Details:
Job Description:
Key Responsibilities:
Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies.
Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies.
Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP.
Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits.
Mentor and technically guide a team of junior and senior designers.
Review and approve specifications, schematics, simulations, and post-layout signoff for high-reliability silicon meeting clock and circuit specs.
Partner with foundries, EDA vendors, and internal silicon validation teams to ensure robust silicon correlation and yield.
Qualifications:
Required Qualifications:
M.Tech / B.Tech / Ph.D. in Electrical/Electronics Engineering or related field.
15–20 years of hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.
Proven expertise in clock tree synthesis (CTS), clock gating, low-power techniques, and glitch-free clock domain crossing.
Deep experience with PLL/DLL architecture, design, and integration in SoCs.
Strong background in transistor-level design, spice simulations, and post-layout validation.
Familiarity with EDA tools and scripting (TCL, Perl, Python).
Experience leading multi-disciplinary teams and working across global sites.
Excellent communication, documentation, and project leadership skills.
Preferred Qualifications:
Background in high-speed interface IPs, power management circuits, or custom memory design.
Experience with Server, AI/ML, or networking SoCs.
Exposure to Silicon bring-up, characterization, and debug.
Previous patents or publications in the area of clocking or circuit design.
Job Type:
Experienced HireShift:
Shift 1 (India)Primary Location:
India, BangaloreAdditional Locations:
Business group:
As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
