Sr. Principal Engineer, Design Technologist

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role:

Title: Sr. Principal Engineer – Design Technology

We are seeking a Design Technologist with deep expertise in design technology, semiconductor process technology, and technology adoption for SoC designs. The main focus of this role is enabling efficient silicon development by aligning design methodologies with foundry technologies, improving PPA (Power, Performance, Area) and enabling cost entitlement, manufacturability

Essential Responsibilities:

• Fab and Process interface working closely with process teams to get a deep understanding of different technology nodes, design rules, technology constraints. Translate the process technology capabilities into design guidelines and methodology improvements that provide best-in-class PPA, Design for Manufacturing (DFM) and yield optimization

• Design technology leadership with deeper understanding of technology and design constraints. Drive technology benchmarking, define and standardize figure-of-merit (FOM) analysis for existing and new technology nodes for technology assessment. Be the champion in evaluating process technology node options for new SoC products

• Cross-collaboration and SoC design enablement leadership working closely with different disciplines in SoC design such as architecture, RTL, and physical design teams to ensure process aware design decisions. Define technology aware design methodologies and sign-off flows for advanced technology nodes taking into consideration PPA targets and DFM goals

• EDA & Design flow optimization develop and improve EDA flows for advanced process nodes. Support implementation flows including synthesis, P&R, timing closure, power optimization and sign-off verification. Work closely with internal methodology and EDA tool vendors to integrate new methodologies and regularly drive internal and external team EDA roadmaps

• Driving benchmarking, roadmap, innovation in the area of design technology. Drive technology benchmarking including competitive analysis and highlight critical architecture, design and technology advantages required for the end products being developed. Address technology node gaps with innovative design techniques, working closely with design team/foundry team in influencing component and product level roadmaps. Drive a culture of strong innovation across power, performance, area and reliability

• Mentorship and leadership in providing technical guidance and mentorship to other junior engineers. Providing technical guidance across teams on topics related to design technologies. Ability to present to senior leadership and drive clarity on technology and design choices

• Customer and partner support leadership to address technical queries, support, and resolve issues related to design technology, PPA and process nodes

• Stay current with the latest trends in semiconductor process nodes and fabrication technologies. Evaluate impact and proactive engagement on emerging trends and technologies including advanced packaging. Be the strategic guide for technology adoption for future SoC design and work closely with process teams in improving the process offerings for future

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications: 

• Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field

• Minimum 15+ years of experience in SoC design, Physical Design, EDA flows/methodologies and/or semiconductor process integration  

• Deep understanding of semiconductor fabrication processes on advanced process nodes, technology PDK and strong understanding of technology development and fab interactions

• Hands-on experience in understanding trade-offs and design understanding of timing, power and signal integrity challenges in modern SoCs. Proven track record of developing SoC implementation flows on advanced technology nodes and clear understanding of design considerations that impact PPA

• Working knowledge and understanding of industry-standard EDA tools for design and simulation such as Cadence, Synopsys, Siemens etc. 

• Strong analytical and debugging skills: Ability to identify, assess, and aid in debugging complex problems

• Excellent communication and documentation skills: Capable of producing clear, comprehensive requirements and architecture documentation for both internal and external usage 

• Collaborative mindset: Comfortable working in global, cross-disciplinary teams and engaging directly with customers and partners 

Preferred Qualifications:

• Experience in working with yield analysis and silicon bring-up

• Experience in advanced packaging or chiplet architecture