Job Details:

Job Description:

We are seeking an innovative Soft CPU Design Engineer to join our IP Engineering team at our Altera Headquarters in San Jose, CA. In this specialized role, you will be responsible for the micro-architecture, RTL design, and implementation of high-performance, area-efficient Soft CPU cores. Unlike traditional ASIC design, your focus will be entirely on architecting processor pipelines that are natively optimized to leverage Altera FPGA architectures (including ALMs, embedded memory blocks, and DSP slices). You will directly shape the future of Altera's embedded processor roadmaps, such as our RISC-V-based Nios V ecosystem, enabling customers to deploy flexible, high-efficiency processing directly into programmable logic.

Key Responsibilities

• FPGA-Targeted RTL Design: Micro-architect, design, and implement Soft CPU cores (using SystemVerilog/Verilog) intentionally structured to map efficiently onto Altera FPGA architectures 
• PPA Optimization for Programmable Logic: Maximize Performance, Power, and Area (PPA) by optimizing processor pipelines around FPGA-specific constraints, utilizing Adaptive Logic Modules (ALMs), M20K/MLAB memory blocks, and specialized DSP columns.
• FPGA Synthesis & Timing Closure: Drive the design through Altera’s proprietary tool flows , managing floorplanning, placement constraints, and aggressive timing closure at high frequencies.
• Customization & Extensibility: Implement features allowing for highly configurable soft cores, including optional instruction set extensions, custom instructions, and variable cache configurations.
• Verification & Validation: Collaborate with Design Verification (DV) teams to build robust simulation environments and actively participate in hardware validation using Altera development boards.

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. 

$133.2K - $192.8K USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Required Skills & Qualifications

• Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Core Experience: 3+ years of digital design experience with a specific focus on CPU/Processor RTL design and FPGA implementation.
• Languages: Advanced proficiency in SystemVerilog or Verilog for FPGA synthesis.
• Architectural Knowledge: Strong understanding of processor pipeline design, hazard handling, branch prediction, and memory hierarchy (caches, tightly-coupled memories).
• FPGA Tooling: Deep hands-on proficiency with Altera Quartus Prime Pro, including advanced components like Platform Designer (Qsys), TimeQuest Timing Analyzer, and Signal Tap or similar EDA software.

Preferred Qualifications

• In-depth familiarity with the open-source RISC-V ISA specification and custom instruction insertion.
• Experience with standard FPGA on-chip interfaces like Avalon Memory-Mapped / Streaming and AMBA AXI interfaces.
• Knowledge of compiler toolchains (GCC, LLVM), assembly programming, and embedded C debugging.
• Proficiency in Python, Tcl, or Shell scripting to automate FPGA compilation and regression workflows.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.