CPU Architecture Performance Engineer, Senior to Staff Level

Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc. Verify performance feature between RTL and model, and have ability to troubleshooting Work with design team and performance team to develop test case and validate new feature MS degree in Computer Architecture with 3-5 years of practical experience Good CPU architecture knowledge and micro-architecture knowledge Experience working in a RTL simulation environment Experience working in a performance modeling environment Proficient in Verilog, C and C++ and scripting languages such as Perl or Python Ability to problem solve and prove your own ideas Knowledge and experience with common performance benchmarks and workloads Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.